1. Field of the Invention
The present invention relates to a matrix type display device that uses electric current as transmitting signal, and a driving method thereof.
2. Description of the Related Art
The matrix type display device such as a liquid crystal display device and a plasma display panel (also referred to as PDP) is provided with a display controller that sequentially outputs image data, a source driver that generates a drive signal for driving a display panel based on the image data output from the display controller, and a display panel that displays an image by the drive signal.
In such a display device, the signal between the display controller and the source driver has conventionally been transmitted by a voltage signal that consists of two values of power source potential and earth potential. However, parasitic capacitance of transmission path causes delay if the voltage signal is made to be high-speed, and the level of high-speed voltage signal is limited.
The applicant then developed a technique of transmitting a signal by electric current, which is disclosed in Japanese Patent Application Laid-open No. 2001-053598. This technique restricts the affect of the parasitic capacitance of the transmission path, and the high-speed signal can be realized. Further, Japanese Patent Application Laid-open No. 2001-053598 also discloses a technique that a power source is not provided for a transmission section but for a receiving section. Thus, it is not necessary to change the specification of the transmission section even if the number of the receiving sections is changed, and the design of the transmission section becomes easy.
Specifically, a pair of wirings for transmitting signal is provided between the transmission section and the receiving section. Then, in the transmission section, one of the wirings is connected to an earth electrode and the other wiring is set to a floating state (high-impedance state) based on a signal intended to transmit. Accordingly, electric current flows from the power source provided for the receiving section to the earth electrode via the wiring connected to the earth electrode and the electric current does not flow to the other wiring. As a result, it is possible to transmit a complementary signal by a pair of the wirings. The applicant has named the transmission method as CMADS (Current Mode Advanced Differential Signaling).
FIG. 1 is a block diagram showing a conventional liquid crystal display device for which the CMADS was applied. As shown in FIG. 1, the conventional liquid crystal display device is provided with a display controller 101, a source driver 102, and a liquid crystal panel 103. Further, two pairs of wirings 104a and 104b, 105a and 105b are provided between the display controller 101 and the source driver 102.
The display controller 101 is one to which image data as digital two-value voltage signal is input from outside and that outputs the image data by every line. The display controller 101 is provided with a display data memory 106, a timing control circuit 107, a V-I conversion circuit for image data 108, and a V-I conversion circuit for clock signal 109. The display data memory 106 is one to which the image data is input from outside and that holds the image data for one screen. The timing control circuit 107 reads out the image data equivalent to one line from the display data memory 106, outputs a clock signal to the V-I conversion circuit for clock signal 109, and sequentially outputs the image data equivalent to one line to the V-I conversion circuit for image data 108 synchronously with the clock signal. The V-I conversion circuit for image data 108 is connected to one end of a pair of the wirings 104a and 104b, in which either one of the wirings 104a and 104b is connected to the earth electrode and the other wiring is set to the floating state based on the image data. The V-I conversion circuit for clock signal 109 is connected to one end of a pair of the wirings 105a and 105b, in which either one of the wirings 105a and 105b is connected to the earth electrode and the other wiring is set to the floating state based on the clock signal.
Furthermore, the source driver 102 is provided with an I-V conversion circuit for image data 121, an I-V conversion circuit for clock signal 122, a shift register 123, a data latch circuit 124, a gradation selecting circuit 125, and an output circuit 126. The I-V conversion circuit for image data 121 is connected to the other end of a pair of the wirings 104a and 104b. Then, when the V-I conversion circuit for image data 108 connects either one of the wirings 104a and 104b to the earth electrode, The I-V conversion circuit for image data 121 allows electric current to flow in the wiring connected to the earth electrode to generate a complementary current signal in a pair of the wirings 104a and 104b. Consequently, the I-V conversion circuit for image data 121 receives the image data as the current signal from the V-I conversion circuit for image data 108. Then, the I-V conversion circuit for image data 121 converts the image data again into the two-valued voltage signal based on the current signal, and outputs the signal to the data latch circuit 124. The I-V conversion circuit for clock signal 122 is connected to the other end of a pair of the wirings 105a and 105b. Then, when the V-I conversion circuit for clock signal 109 connects either one of the wirings 105a and 105b to the earth electrode, the I-V conversion circuit for clock signal 122 allows electric current to flow in the wiring connected to the earth electrode to generate the complementary current signal in a pair of the wirings 105a and 105b. Consequently, the I-V conversion circuit for clock signal 122 receives the clock signal as the current signal from the V-I conversion circuit for clock signal 109. Then, the I-V conversion circuit for clock signal 122 converts the clock signal again into the two-valued voltage signal based on the current signal, and outputs the signal to the shift register 123.
The shift register 123 is one to which the clock signal is input and that sequentially outputs pulse signals from a plurality of output terminals to the data latch circuit 124. The data latch circuit 124 downloads a plural image data synchronously with the pulse signals to output a plurality of the image data to the gradation selecting circuit 125 simultaneously. The gradation selecting circuit 125 is a D/A converter, which performs digital-analog conversion (D/A conversion) to the output signal from the data latch circuit 124 and outputs a gradation signal that is an analog voltage signal to an output circuit 126. The voltage of the gradation signal is a voltage applied for each pixel of the liquid crystal panel 103. The output circuit 126 performs current amplification to the gradation signal to generate a drive signal, and outputs the drive signal to each pixel of the liquid crystal panel 103.
Moreover, the liquid crystal panel 103 is provided with two transparent substrates (not shown) arranged facing with each other, a liquid crystal layer (not shown) sandwiched between the transparent substrates, and a backlight (not shown) arranged behind the two transparent substrates. Further, pixels (not shown) are arranged in a matrix state on the liquid crystal panel 103.
Next, description will be made for the operation of the conventional liquid crystal display device. Firstly, the image data as the two-valued voltage signal is input to the display data memory 106, and the data equivalent to one screen is held. Then, the timing control circuit 107 reads out the image data equivalent to one line from the display data memory 106. The timing control circuit 107 then outputs the clock signal that is the two-valued voltage signal to the V-I conversion circuit for clock signal 109. Further, the timing control circuit 107 sequentially outputs the image data to the V-I conversion circuit for image data 108 synchronously with the clock signal.
Next, the V-I conversion circuit for image data 108 connects one end of a pair of the wirings 104a and 104b to the earth electrode and sets the other wiring to the floating state based on the image data. For example, the wiring 104a is connected to the earth electrode and the wiring 104b is set to the floating state when the image data is high, and the wiring 104a is set to the floating state and the wiring 104b is connected to the earth electrode when the image data is low. Further, the V-I conversion circuit for clock signal 109 connects one end of a pair of the wirings 105a and 105b to the earth electrode and sets the other wiring to the floating state based on the clock signal.
Accordingly, the I-V conversion circuit for image data 121 allows electric current to flow in either wiring of a pair of the wirings 104a and 104b, which is connected to the earth electrode. The electric current flows from the I-V conversion circuit for image data 121 to the earth electrode via the wiring 104a or 104b. On the other hand, the electric current does not flow in the wiring on the floating state. As a result, the image data that is the voltage signal is converted into a pair of complementary current signals, and is transmitted from the V-I conversion circuit for image data 108 to the I-V conversion circuit for image data 121 via a pair of the wirings 104a and 104b. Then, the I-V conversion circuit for image data 121 converts the current signal into the two-valued voltage signal again to regenerate the image data, and outputs the data to the data latch circuit 124.
Similarly, the I-V conversion circuit for clock signal 122 allows the electric current to flow in either wiring of a pair of the wirings 105a and 105b, which is connected to the earth electrode. On the other hand, the electric current does not flow in the wiring on the floating state. As a result, the clock signal that is the voltage signal is converted into a pair of complementary current signals, and is transmitted from the V-I conversion circuit for clock signal 109 to the I-V conversion circuit for clock signal 122 via a pair of the wirings 105a and 105b. Then the I-V conversion circuit for clock signal 122 converts the current signal into the two-valued voltage signal again to regenerate the clock signal, and outputs the signal to the shift register 123.
The shift register 123 downloads the clock signal from the I-V conversion circuit for clock signal 122, and sequentially outputs the pulse signal from a plurality of output terminals to the data latch circuit 124. The data latch circuit 124 downloads a plurality of image data from the I-V conversion circuit for image data 121 synchronously with the pulse signal, and simultaneously outputs a plurality of the image data to the gradation selecting circuit 125. Next, the gradation selecting circuit 125 performs D/A conversion to the output signal to generate the gradation signal that is the analog voltage signal, and outputs the signal to the output circuit 126. Then, the output circuit 126 performs current amplification to the gradation signal to generate the drive signal, and applies it to each pixel of the liquid crystal panel 103.
On the other hand, in the liquid crystal panel 103, the backlight irradiates light to each pixel. Then, the liquid crystal layer of each pixel changes transmission factor of light according to the voltage of the drive signal applied, forms an image as the entire liquid crystal panel 103.
However, the above-described prior art has the following problems. Recently, a small display device such as a cellular phone in particular is normally equipped with a function such as a subtractive color mode to economize image data amount. The function subtracts colors of the image data from 260,000 colors to 8 colors, for example, and thus reducing the image data amount from 18 bits to 3 bits. In addition, a technique to encode and compress the image data has generally been used.
In the case of reducing the image data amount, dummy transfer is performed in signal transfer between the display controller and the source driver other than the data necessary for displaying the image. At this point, when the image data is transmitted by the voltage signal as conventionally performed, power consumption can be reduced by reducing the image data amount. However, when the image data is transmitted by the current signal, the electric current continuously flows in the wiring between the display controller and the source driver during the dummy transfer, and there exists a problem that the effects to reduce the power consumption is not obtained.